1. Field of the Invention
The invention relates to electrical communications systems with storage of signals in general and more specifically to integrated circuit read only memories.
2. Description of Prior Art
Some of the conventially known memory word line addressing methods include incrementing a binary address counter each time a next word line is to be energized. The binary outputs from the counter are decoded in order to energize each individual word line. Another technique which has been employed is to provide a ring counter having a different stage connected to each word line.
One of the substantial disadvantages of separate addressing counter means for addressing an integrated circuit is that substantial substrate surface area is required just to make the wiring connections between the counter and the memory array. An additional disadvantage is that each wiring connection is subject to a statistical probability of causing a circuit failure; therefore the substantial number of wiring connections required to connect an address counter to a memory array substantially reduces the integrated circuit production yield and reliability.
Further disadvantages which arise when utilizing address counters to address a memory array are the complex and special counter circuit connections which are required to perform a branch and to perform a branch-on condition function.